Case File2017
Hardware-Security ASIC Validation Platform
NYU Abu Dhabi · with Ozgur Sinanoglu's hardware-security group
Challenge, contribution, and outcome
CHALLENGE
The hardware-security group needed a reliable PCB test rig to validate logic-locked 65 nm ARM Cortex-M0 silicon before ACM CCS publication.
MY CONTRIBUTION
Led electronics design and fabrication of the ASIC validation PCB — schematic, layout, in-house fabrication, and silicon bring-up for the ACM CCS 2017 logic-locking work.
OUTCOME
Validated locked processor silicon on the custom board: correct execution with the valid key, failure with an incorrect one.
Narrative
Led PCB development and hardware bring-up of a custom test platform for a 65 nm ARM Cortex-M0 logic-locked ASIC — UART programming, key activation, and silicon validation for ACM CCS 2017.
System Record
- Application
- APPHardware Security
- Laboratory
- Platforms
- PLATFORMCustom PCB / ASIC Test Rig
- Methods
- METHODPCB Design
- Outcomes
- OUTCOMEPeer-Reviewed Publication
- Period
- 2017
Development & Validation
- Eagle schematic, two-layer layout, and in-house fabrication on NYUAD Core Technology Platform equipment — two revisions to a reliable UART/DIP-switch test rig.
- Validated locked processor silicon: correct execution with the valid key, failure with an incorrect one.
Credits & Collaborators
Nikolaos Giakoumidis
NYU Abu Dhabi
Electronics design · hardware validation
Ozgur Sinanoglu
NYU Abu Dhabi · Hardware Security Group
Principal Investigator
Hardware Security Group
NYU Abu Dhabi
Research partner
Related
Publications
- Provably-Secure Logic Locking: From Theory to Practice
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (CCS) · 2017
Photos
SOP-28 SOCKET — LOCKED PROCESSOR UNDER TEST